A technique has been proposed in which a plurality of virtual machines operating on a server are individually coupled to field-programmable gate arrays (FPGAs) mounted on an FPGA board such that data processing is executed at a high speed.
Another technique has been proposed in which one of servers that execute software functions and one of FPGAs that execute hardware functions are coupled to each other by a coupling unit such that data processing is executed by the server and the FPGA.
A further technique has been proposed in which one of servers and a graphics processing unit (GPU) or an FPGA that functions as an accelerator are switchably coupled to each other by a switch that is controlled by a management server.
An emulator has been proposed which programs logics of an emulation target in an FPGA mounted on a resource board together with a memory and so forth and emulates operation of an electronic apparatus.
As examples of the related art, Japanese National Publication of International Patent Publication No. 2015-507234, Japanese Laid-open Patent Publication No. 2013-45219, Japanese Laid-open Patent Publication No. 2013-196206 and Japanese Laid-open Patent Publication No. 2005-11344 are known.